High-speed latches can be used to build sophisticated digital processing systems, such as those used to process microwave signals. These latches store digital data under the action of a clock signal. Where the clock signal has a high frequency, for example above 1 GHz and up to 500 GHz or more, one known type of latch has two resonant tunneling diodes (RTDs), which are coupled in series and which operate at GHz clock rates with very low power consumption.
In these known latch circuits, the series-coupled RTDs receive electrical power from a current-limited voltage source, which may for example be a battery and two resistors. The data input signal may be supplied to the latch through a resistor coupled to the node between the RTDs. A reset circuit is normally coupled across the series-connected RTDs. For example, where the two RTDs are coupled in series between first and second nodes, one known reset circuit has a simple field effect transistor (FET) with its source and drain respectively coupled to the first and second nodes, and has a clock signal which is applied to the gate of the FET. The voltage of the clock signal varies in a periodic manner over time, so that the electrical resistance of the drain-to-source path through the FET alternates between a highly resistive state and a highly conducting state. When the FET is in its highly conducting state, the potential difference between the drain and source terminals of the FET, which is also the potential difference between the outer nodes of the series-coupled RTDs, drops to a value sufficient to force the voltage across both RTDs to a low or “off” state. When the latch is in this state, it is said to be reset.
When the clock signal changes state and causes the FET to change to its highly resistive state, the voltage across the series-coupled RTDs rises until one or both of the RTDs switches to a high voltage or “on” state. The final electrical state of the RTDs is determined by the polarity of the electrical current which is being provided to the latch by the data input signal at the moment in time when the FET transitions from its highly conducting state to its highly resistive state. Thus, this circuit configuration provides an edge sensitive clocked digital latch.
Although this configuration has been generally adequate for its intended purpose, it has not been satisfactory in all respects. For example, one disadvantage is that the dynamic gate current of the FET is effectively introduced into the operation of the latch circuit, which is a phenomenon commonly known as “clock injection”. In more detail, as the voltage of the clock signal varies over time, a displacement current is produced at the gate of the FET, and is proportional to the rate of change of the clock signal voltage. This current passes through the drain and source nodes of the FET and into the RTD circuitry, and can upset the normal electrical balance of the latch, which in turn prevents the latch from accurately capturing the value of the data input signal. This disadvantageous effect of clock injection increases with the frequency of the clock, so that the known latch circuit is limited in its frequency of operation by the effect of clock injection.